Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased packing density, therefore increased net die per wafer (numbers of usable chips produced from a standard semiconductor wafer). To meet these requirements, semiconductor manufacturers have been forced to build new fabrication lines at the next generation process node (gate length). As the critical dimensions for these devices grow smaller, greater difficulties will be experienced in patterning these features using conventional photolithography.
Conventional photolithography methods used for pattern generation involve exposing a light sensitive photoresist layer to a light source. The light from the source is modulated using a reticle, typically a chrome on quartz mask. The patterns formed on the reticle are transferred to the photoresist layer using typically visible or ultraviolet light. The areas so exposed are then developed (for positive photoresist) or, alternatively, the unexposed areas are developed for negative type photoresist. The developed regions are then washed away and the remaining photoresist pattern used to provide an etching mask for the substrate.
One approach to achieving the desired critical dimensions has been to use attenuated phase shift masks and strong phase shift masks. Although useful such masks suffer from a number of shortcomings. For one, a mask set for such phase shift masks takes a long time to make. Sometimes these mask sets can take thirty days or longer to manufacture. Additionally, such mask sets are particularly vulnerable to defects which can have catastrophic effects on the reticle yield. Also, due to the etch processes used in making such masks, there are numerous non-uniformities in surface conformation. These result in unwanted and unexpected diffraction and scattering patterns which interfere with and corrupt the desired light pattern produced with these masks. Additionally, the interactions between light and the sidewalls present in such masks create their own wave patterns which interfere with and corrupt the desired light pattern produced with these masks. Additionally, because such phase masks require at least two exposures per layer and because many process layers are commonly used to form modern semiconductor structures, alignment difficulties between the masks and the wafer comprise significant process complications. Additionally., imperfections in mask feature size, feature placement, phase, or transmission cannot be easily inspected and repaired.
These complications result in costs that are disproportionate to the costs involved in other aspects of the chip fabrication. This is particularly significant when the chip is an application specific integrated device with only a small production lot desired. Additionally, it is a substantial effort to make small changes in the design once the masks are fabricated. This is particularly important because often the design of the chip must be modified after testing of chips produced from the first mask set. This results in additional expenditures for second, third, and even more sets of masks. Finally, with the reduction in feature sizes, various process limitations in the conventional lithography process have made IC fabrication more difficult.
X-ray and electron beam lithography have been proposed (and adopted in some instances) for imaging very small features. This is because the radiation employed in these techniques has much shorter wavelengths than the ultra-violet radiation employed in conventional photolithography. However, x-ray lithography has found only limited acceptance because of mask, source and resist technology problems. Sources have not been sufficiently bright, and resists have not been adequately sensitive or process-resistant. Further, x-ray masks can be complex to manufacture and current process difficulties (such as the presence of a nonzero mask to wafer gap) do not permit resolution consistent with the theoretical limits set by wavelength. For at least these reasons, x-ray lithography has not gained widespread acceptance.
Electron-beam lithography (referred to herein as e-beam lithography) has also been proposed. E-beam lithography involves exposure of a radiation sensitive film to a beam of focused electrons in a vacuum, followed by development of the resist film, and subsequent etching. Thus, e-beam lithography includes the basic steps of conventional lithography, but substitutes a scanning electron beam for an ultraviolet source and reticle. Unfortunately, the imaging step of e-beam lithography is relatively slow. Rather than exposing an entire IC to an image in one shot (as is done in conventional optical lithography), e-beam lithography requires that an electron beam be scanned over the IC wafer surface in a rasterized fashion. To produce a thin line, an e-beam sometimes must be scanned over the line multiple times because the beam size is quite small. This combination of raster scanning and multiple passes requires a long time to produce a pattern image. Thus, e-beam lithography fabrication processes have a relatively low throughput.
Thus, the numerous present art lithography and chip fabrication processes have numerous disadvantages. As critical dimensions decrease these problems and the costs inherent in solving them will only increase.
In view of the above difficulties, what is needed is a relatively fast and inexpensive approach for transferring images of very thin line width to a wafer. In other words, an effective solution to rising mask costs and processing difficulties is needed.